The present invention relates to a method and apparatus for multiplexing digital signals by using a frame synchronizing signal of one channel as a frame synchronizing signal of a multiplexed digital signal when a plurality of digital signals having the same bit rate are multiplexed in digital signal processing.
In conventional digital multiplexing, a plurality of low-speed signals having a given bit rate are multiplexed to give a high-speed signal. In this case, since multiplex data is added to the transmission data, the bit rate of the multiplexed transmission data does not become an integer multiple of the bit rate of the low-speed signal. This will be described with reference to FIG. 1. FIG. 1 shows an example wherein two digital signals are multiplexed. Reference symbols A and B denote two digital signals of a given bit rate. Reference symbols a.sub.0-7, a.sub.0-8, . . . , a.sub.2-5, a.sub.2-6, b.sub.0-5, b.sub.0-6, . . . , b.sub.2-3 and b.sub.2-4 denote data bits, respectively; and F, a frame synchronizing signal. The frame synchronizing signals F are set in an alternating pattern of logic "0" and logic "1". The signals A and B have an identical frame format. Reference symbol C denotes a multiplexed signal. Reference symbols a and b of the multiplexed signal format denote data bits of the signals A and B, respectively. A frame synchronizing signal Fa of the multiplexed signal corresponds to the frame synchronizing signal F of the signal A or B and indicates the multiplexed relationship between the signals A and B. The frame synchronizing signal Fa of the multiplexed signal is required at the time of demultiplexing. When the bit rate of the signals A and B is given to be f bits/sec (b/s), two frame synchronizing signals are included for every 20 bits of the multiplexed signal C. Therefore, the bit rate of the multiplexed signal is calculated to be (f x 20/9) b/s.
FIG. 2 is a block diagram of a multiplex circuit which realizes the function described above. A clock generator 1 comprises a quartz crystal oscillator for oscillating clocks or a circuit for generating clocks in response to externally supplied clocks. Reference numeral 2 denotes a 1/20 frequency divider for frequency-dividing the clock with a frequency division ratio of 1/20; 3, a VCO (voltage-controlled oscillator) for oscillating at a frequency about f Hz; 4, a 1/9 frequency divider; and 5, a phase comparator. The VCO 3, the 1/9 frequency divider 4 and the phase comparator 5 constitute a PLL (phase-locked loop). A 1/9 frequency-divided clock from the VCO 3 is phase-locked with a 1/20 frequency-divided clock from the clock generator 1. Therefore, if the frequency of the clock generator 1 is given to be fa Hz, a relation f.times.1/9=fa.times.1/20 is satisfied. Serial-parallel converters 6 and 7 convert serial inputs 10 and 9 to 9-bit parallel data by using the frequencies f Hz and (f.times.1/9) Hz, respectively. A multiplexer 8 receives 9-bit outputs (i.e., 18-bit parallel signals) from the serial-parallel converters 6 and 7 and a frame synchronizing signal input 11 and converts the input signals to a serial multiplexed signal 12. When the alternating pattern of logic "1" and logic "0" is used for frame synchronization, every other signal Fa is used as a frame synchronizing signal, the remaining signals Fa can be used for another purpose. In this case, two frame synchronizing bits can be used as the frame synchronizing signal input 11 for every 20 bits of the multiplexed signal. However, according to the multiplexing described above, 9/20 frequency division must be performed, and so the multiplex circuit becomes complicated, and the control of phases between the signals is difficult. Since a complex demultiplex circuit is also required, the overall circuit arrangement becomes complicated, resulting in inconvenience.